This invention relates generally to implantable medical devices, and more particularly to an improved operating system architecture incorporating adiabatic clock-powered logic, alone, or in conjunction with self-timed logic, for reducing power consumption and increasing and improving processing capabilities.
A wide variety of implantable medical devices (IMDs) that employ electronic circuitry for providing electrical stimulation of body tissue and/or monitoring a physiologic condition are known in the art. A number of IMDs of various types are known in the art for delivering electrical stimulating pulses to selected body tissue and typically comprise an implantable pulse generator (IPG) for generating the stimulating pulses under prescribed conditions and at least one lead bearing a stimulation electrode for delivering the stimulating pulses to the selected tissue. For example, cardiac pacemakers and implantable cardioverter/defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of malignant tachyarrhythmias. Other IMDs have been developed for applying electrical stimulation or other therapies, e.g., drugs, to nerves, the brain, muscle groups and other organs and body tissues for treating a variety of conditions.
Over the past 40 years, such IMDs have evolved from relatively bulky, crude, and short-lived devices providing simple stimulation therapies and monitoring functions to complex, long-lived, and miniaturized IMDs, e.g., cardiac IMDs providing a wide variety of pacing and/or cardioversion and defibrillation therapies and/or monitoring functions. Numerous other programmable functions have been incorporated including enhanced capacity to detect and discriminate cardiac arrhythmias, to store data and to uplink telemetry data related to arrhythmia episodes and applied therapies (if any). Moreover, the capability of interrogating stored device data and initiating real time uplink telemetry of physiologic data, e.g. the real time cardiac EGM and blood pressure and the like, have been incorporated into such IMDs.
The earliest implantable pacemaker IPGs employed very simple analog circuit oscillators formed by discrete transistors and other circuit components and were very short-lived and electrically inefficient. Integrated circuit (IC) technology and battery improvements were made that enabled hermetic sealing of IMD housings, improved reliability and lengthened the operating life of the IMD. The MEDTRONIC(copyright) SPECTRAX(copyright) pacemaker IPGs incorporated an analog IC with digital IC into a digital clocked logic operating system architecture providing an array of sophisticated operating functions, programmability of operating modes and parameters, data storage, and uplink telemetry functions. Successive generations of IMDs of this type have incorporated increased operating modes and functions through further improvements in circuitry and long-lived, low current output, low voltage batteries. Most recently, a wide number of IMD system architectures have been developed that incorporate custom microcomputers comprising a microprocessor, RAM and ROM, bus, and related elements of a typical microcomputer and other control logic, memory, input signal processing circuitry and therapy delivery output circuitry. The complexity of the circuitry, the functions provided, the longevity, and the reliability of the IMDs have all increased dramatically while the IMD size has decreased.
Current IMD operating system architectures typically are embodied in two or more ICs and discrete components mounted to one (or more) substrate employing hybrid fabrication circuitry techniques. Certain of the ICs or circuitry on a particular IC perform analog functions, input signal processing, and output therapy delivery. Digital logic ICs or circuitry are formed employing complementary metal oxide semiconductor (CMOS) fabrication technology. The digital logic ICs perform signal processing, timing, and state change functions embodying Boolean logic timed synchronously by a system-wide, clock, and are referred to herein as xe2x80x9cclocked logicxe2x80x9d ICs or circuits.
The power consumption of CMOS circuits consists generally of two power consumption factors, namely xe2x80x9cdynamicxe2x80x9d power consumption and xe2x80x9cstaticxe2x80x9d power consumption. The static power consumption is only due to current leakage, as the quiescent current of such circuits is zero. Dynamic power consumption is due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances, and is the dominant form of power consumption for CMOS technology. The dynamic power (P) for the CMOS circuit is a function of nodal capacitance (C), the clock or switching frequency (F), and the supply voltage (VDD) in accordance with the formula P=C VDD2F.
By way of explanation, reference is made FIG. 1, which shows a simple CMOS buffer circuit 10 operated using a dual rail clock xc3x8 to provide a logic level output at node 22 that is inverse to the applied input. A logic level input signal is provided to the gate terminals of a P-channel MOS (pMOS) FET 14 and N-channel MOS (nMOS) FET 16, the dual rail clocks are is applied to the gate terminals of a pMOS FET 12 and nMOS FET 18. Load capacitor 20 is coupled between the node 22 at the source and drain terminals of the pMOS and nMOS FETs 18 and 12. As will be appreciated, the pMOS FET 14 is biased to switch ON and the nMOS FET 16 is biased to switch OFF when the input is driven LOW, and, conversely, the pMOS FET 14 is biased to switch OFF and the nMOS FET 16 is biased to switch ON when the input is driven HIGH. The nMOS FET 12 is biased to switch ON by the clock xc3x8 applied to its gate, and the pMOS FET 18 is biased to switch ON by the inverted clock xc3x8 applied to its gate.
The pMOS FET 14 and pMOS FET 18 both switch ON only when the input is driven LOW and when the inverted clock xc3x8 occurs. The capacitor 20 is then charged from the voltage source VDD, and a logical one (HIGH) is registered at the output (node 22).
Similarly, the nMOS FET 16 and nMOS FET 12 both switch on only when the input is driven LOW and when the clock xc3x8 occurs. The charge stored in the capacitor 20 is then discharged through the nMOS FETs 16 and 12 ground, whereby a logical zero (LOW) is registered at node 22.
Each transition of the input signal to LOW during the inverted clock xc3x8 thereby results in the transfer of a certain amount of energy from the battery supplying VDD to capacitor 20, and that energy is then simply dissipated when the input signal switches HIGH and the clock xc3x8 occurs. In addition, the clock energy is itself dissipated during each clock cycle. Thus, in conventional CMOS switches, such as those shown in FIG. 1, each transfer of charge is coupled with the dissipation of a certain amount of power (P) in accordance with the above formula.
Efforts have been made conventionally in CMOS IC designs used in IMDs to scale down the supply voltage for an entire device (e.g., a hybrid or IC) to provide the minimally required power to reliably operate all of the clocked logic of the device. For example, in the Medtronic SYMBIOS(copyright) pacemaker IPGs, the logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a xe2x80x9csum of thresholdsxe2x80x9d supply. This regulator provided a supply to the IC (i.e., VDD) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds. This same approach of specifying a high enough voltage to account for fabrication variances is followed even when only a single such CMOS IC is employed in the IMD system. Therefore, in practice, excessive power may be consumed by the CMOS IC or ICs of the IMD operating system.
Other IMDs have reduced power consumption in other varied manners, e.g., by shutting down analog blocks and/or shutting off clocks to logic blocks not being used at particular times. In commonly assigned U.S. Pat. No. 5,916,237, it is proposed that the power delivered to selected sections of the digital logic circuitry in IMDs be cycled between power ON and power OFF states to reduce static power consumption. In many applications, most of the digital logic circuitry may be turned off at various times during each system clock cycle, which reduces static power consumption and average power consumption of the is digital clocked logic circuitry.
In addition, microprocessor based IMDs provided by virtually all pacemaker and ICD manufacturers have historically used a xe2x80x9cburst clockxe2x80x9d design to perform processing operations at a relatively high clock rate (e.g., generally 500-1000 KHz) for relatively short periods of time to gain the benefit of a xe2x80x9cduty cyclexe2x80x9d to reduce average current drain. A much lower frequency clock (e.g., generally 32 KHz) is used for other timing and control circuitry and/or the processor when not in the high clock rate, burst clock mode. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. Nos. 4,561,442, 5,022,395, 5,154,170, and 5,388,578.
These approaches to reducing the dynamic power dissipation can be summarized as reducing the operating voltage VDD to the lowest level ensuring reliable operation, reducing the capacitance C, and reducing the number of switching operations which occur within an IC over a set time period. Even with these improvements, clocked logic CMOS circuits assembled from logic gates, flip-flops, and other Boolean logic blocks used in IMD system architectures suffer from several limitations and disadvantages.
Recently, the concept of using adiabatic logic has been proposed as a method of reducing energy dissipation in IMDs. Simply stated, adiabatic logic, sometimes referred to as xe2x80x9cresonantxe2x80x9d, clock-poweredxe2x80x9d or xe2x80x9cstep-wise charging clocked logicxe2x80x9d seeks to avoid or minimize any energy exchange with the environment, that is dissipation of energy as heat.
A discussion of adiabatic logic principles and alternative circuit implementations appears in chapter 6, entitled xe2x80x9cAdiabatic Switchingxe2x80x9d by L. Svennson, appearing in the book entitled LOW POWER DIGITAL CMOS DESIGN edited by A. P. Chandrakasan and R. W. Broderson (Kluwer Academic Publishers, 1995) for example. The suggestion of using such circuits in IMDs, e.g., cardiac pacemakers, has been made (see xe2x80x9cNew Design Approach Recycles Electrons to Save Powerxe2x80x94Clock-powered Circuits set Efficiency Recordxe2x80x9d appearing in Electronic Engineering Times, 1997, no. 983, page 37), although no implementation has yet appeared.
Adiabatic clock-powered logic requires the use of specialized single phase or multiple phase clocks. When using any sort of clocked logic, it is necessary to route clock distribution over the complete IC chip area as a clock tree of discrete electrical conductors or lines to reach all clocked logic. The clock tree takes up IC chip real estate that could be used to increase device functions or memory capacity, dissipates power as heat, and increases overall power drain of the IC, decreasing useful life of the IMD battery. Complex timing analysis and worst case design analysis and simulation are required in clocked logic circuits to ensure design integrity because of possible clock skew and the resultant timing errors induced by race conditions. Consequently, it would be desirable to minimize the use of IC real estate occupied by the clock tree, to simplify design analysis and simulation of the IMD system architecture, and to decrease power consumption.
For a time, early, large scale and relatively primitive, general purpose computers did not rely upon clocked logic or CMOS circuitry, and instead operated asynchronously. However, clocked computer system architectures replaced the early asynchronous architectures, and computer clock speeds have steadily increased. Increasing the speed at which a digital logic device transitions between logic states, commonly referred to as switching speed, has long been a primary motivation behind many advancements in the semiconductor arts to increase computing and signal processing power. Increasing the switching speed of a clocked logic circuit, however, results in a proportional increase of the dynamic power (P) consumed by the circuitry as it switches more frequently between logic states as described above. The dynamic power (P) is dissipated as heat in high clock rate microprocessors employed in personal computers, necessitating cooling fans and large scale heat sinks to avoid destructive heat buildup.
In recent years, a variety of self-timed or asynchronous logic schemes have been devised in the effort to reduce the reliance upon high speed clocks in very high speed clocked logic circuits used in computing and telecommunications devices. Self-timed or asynchronous logic systems have therefore been proposed to eliminate or minimized clock trees in such high speed ICs for these applications.
Computing power requirements in IMDs have also increased dramatically in recent years while circuitry, batteries and other components have been decreased in size to achieve small sized, long-lived IMDs favored by physicians and patients. It is desirable to continue to reduce size and power consumption and increase and improve processing capabilities of such IMDs.
In accordance with one aspect of the present invention, an IMD system architecture implemented in clocked logic employs adiabatic clock-powered logic to minimize power dissipation for certain functions. For example, certain functions of IMDs require precise timing out of time periods that are measured in terms of milliseconds to hours, days or weeks or precise timing of encoded data signals that are employed in uplink telemetry from the IMD to an external programmer. Such time periods are timed out as multiples of a stable system clock. Adiabatic clock-powered logic is optimal for timing out such time periods and providing time-dependent encoding of RF signal pulses in uplink telemetry signals. Other circuitry of IMDs may also be implemented advantageously using adiabatic clock-powered CMOS logic.
In accordance with a further aspect the present invention, self-timed logic, alternatively called clockless logic or asynchronous logic, is incorporated into the same IC or ICs with adiabatic clocked CMOS logic, and is used in lieu of clocked logic for certain circuits of an IMD system architecture. Preferably, the self-timed logic implements digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages.
The self-timed CMOS logic can be incorporated into the same IC or ICs with adiabatic clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic allows for efficient allocation of chip real estate, and provides manufacturing economies.
The use of self-timed logic with adiabatic clock-powered logic in IMD ICs advantageously reduces dynamic power consumption and dissipation in the remaining clock tree. The diminution of the clock tree makes IC chip real estate available to incorporate further clocked and self-timed logic therein to increase RAM or to add further IMD functional operations. The decrease in dynamic power consumption and the available real estate enables the addition of further features to the IMD operating system while maintaining a desired battery lifetime. The use of self-timed logic circuits reduces complex timing analysis and worst case design analysis and simulation significantly. The adiabatic operation of the adiabatic clock-powered logic reduces its energy consumption, whereby energy consumption of the entire CMOS logic of the IMD is reduced from energy consumed by conventional clocked logic.